The Energy Cost of Keeping AI Fed

When people talk about AI’s appetite for energy, the conversation usually begins with GPUs, moves through cooling, and increasingly reaches for far more ambitious solutions, including small modular nuclear reactors. But as Slip Signal Technologies works with the University of Maryland to move its first SEDL chip from modeling toward physical implementation, we are examining a less visible part of that power bill: what happens every time data moves.

AI systems must keep their processors continuously fed with data. That data travels between processors and memory, across chiplets, through accelerators, over circuit boards, and between servers. Every movement consumes energy. As systems become larger and faster, delivering the right data to the right place at the right time can become as consequential as the computation itself.

The International Energy Agency puts the larger challenge plainly: “There is no AI without energy—specifically electricity for data centres.”

The market is beginning to recognize that the energy equation extends beyond powering processors. Specifically, there is energy and cost wasted when data cannot move efficiently between chips. That is not an isolated engineering concern. It points to a larger shift in the AI hardware race.

The bottleneck is moving

For years, the semiconductor industry focused primarily on making individual processors faster and packing more transistors onto each chip.

But an AI system is no longer one powerful processor working alone. It is an interconnected environment of GPUs, CPUs, memory, networking components, power electronics, and increasingly, multiple specialized dies assembled within the same package. As those systems become more distributed, overall performance depends on how efficiently their components communicate.

Mark Horowitz, a Stanford University electrical engineering professor and one of the semiconductor industry’s leading researchers, summarized the problem in five words: “Data movement dominates energy consumption.”

This is why the industry is investing heavily in high-bandwidth memory, chiplets, advanced packaging, optical interconnects, and new network architectures. The objective is not only to perform calculations faster. It is to keep expensive computing resources supplied with data rather than leaving them waiting.

A powerful processor waiting for data is still consuming power. It is simply not producing useful work. Research into high-performance computing has quantified how large the imbalance can become. In Quantifying the Energy Cost of Data Movement in Scientific Applications, Gokcen Kestor and colleagues projected that moving data through the memory hierarchy could require energy “two orders of magnitude higher” than performing a floating-point operation.

That research predates today’s generative AI boom, but the underlying physics has not become less relevant. AI systems are now moving extraordinary volumes of data through increasingly dense and complex hardware. And faster data movement introduces another challenge that receives far less public attention: electromagnetic behavior.

Every digital signal is also an electromagnetic event

A digital transition may look simple on a diagram: a zero becomes a one. Physically, however, that transition involves voltage and current changing over time. The faster and sharper the transition, the more high-frequency energy it can generate. That energy can travel through circuit traces, power networks, cables, and the surrounding electromagnetic field.

This is one reason clock speed alone does not tell us whether a system will create electromagnetic interference. A device operating at a seemingly modest frequency can still generate significant high-frequency noise if its digital edges are sufficiently abrupt. Now multiply that effect across billions of transitions taking place inside tightly packed AI hardware.

The same design choices used to increase bandwidth and reduce latency can make signal integrity, electromagnetic compatibility, and power integrity more difficult to manage. Chips are being placed closer together. More data is moving through smaller spaces. Power density is rising. Tolerance for delay is shrinking.

Under those conditions, power, performance, and electromagnetic compatibility stop being separate engineering problems. They become different expressions of the same system.

The traditional answer carries its own cost

When interference appears late in development, engineers have an established toolkit: shielding, filters, additional grounding, greater spacing, redesigned circuit boards, and changes to enclosures or cables. These techniques can be effective. But they are not free.

They can add weight, occupy board space, increase the bill of materials, complicate manufacturing, and trigger another round of testing. In some cases, teams must reduce performance simply to bring emissions under control.

For a consumer device, that may mean a delayed launch or a more expensive enclosure. For a data center, the effects can extend across thousands of densely packed systems. For a drone, vehicle, medical device, or satellite, every additional gram, watt, and square millimeter matters.

This creates a largely invisible form of infrastructure overhead. The industry pays for electromagnetic interference through hardware, engineering time, testing, energy consumption, and lost design flexibility—yet rarely treats those costs as part of the original architecture. They usually appear later, under another budget line.

What if the intervention started earlier?

Most EMI mitigation is applied after a digital signal has already generated unwanted high-frequency energy. Slip Signal Technologies is exploring a different question: can the transition itself be shaped so that the circuit produces less problematic electromagnetic energy at the source? That is the premise behind Spectrally Efficient Digital Logic, or SEDL.

The work mentioned at the beginning of this article has now advanced to a defined digital-input-to-digital-output signal path. The necessary circuit blocks are being integrated into the chip design ahead of fabrication. The meaningful test will come after the silicon returns. The plan is to operate comparable hardware with and without SEDL and measure the difference under controlled conditions.

That process matters because new semiconductor technologies should not be judged by attractive simulations or broad claims. They should be judged by measurable behavior in physical hardware. We are not assuming the answer in advance. We are building the experiment needed to obtain it.

AI’s power problem is a systems problem

AI infrastructure is already placing extraordinary pressure on power generation, transmission, and data-center design. The United States could face a substantial electricity shortfall as AI-related demand grows, even as newer architectures deliver more computing performance. Proposed responses now extend beyond efficiency improvements and grid upgrades to behind-the-meter nuclear generation. More efficient processors will help. Better cooling will help. New energy sources will help.

But efficiency cannot be evaluated only by counting operations per watt. We must also examine what it costs to move the data, preserve signal integrity, control emissions, and compensate for unwanted electromagnetic effects throughout the system.

The next generation of computing infrastructure will depend on more than faster chips. It will depend on how those chips communicate, how much energy that communication consumes, and how cleanly the underlying signals behave.

AI’s appetite continues to grow. The cost of keeping it fed will depend increasingly on what happens between the chips.

Sources

• International Energy Agency, Energy and AI, 2025.

• Mark Horowitz, Computing’s Energy Problem (and What We Can Do About It), 2014 IEEE International Solid-State Circuits Conference.

• Gokcen Kestor et al., Quantifying the Energy Cost of Data Movement in Scientific Applications, 2013 IEEE International Symposium on Workload Characterization.