Power Goes Backside. Noise Doesn’t Disappear.

Power Goes Backside. Noise Doesn’t Disappear.

Backside power delivery is usually described as a solution for two of advanced chip design’s hardest problems: voltage droop and frontside routing congestion. A new research preprint points to the other side of that architectural change.

When the power-and-ground network moves behind the transistors, the frontside metal structures that once separated signal wires may no longer provide the same shielding. The result, according to researchers from the Chinese University of Hong Kong and Peking University, can be greater coupling between adjacent nets and degraded signal integrity.

The July 15, 2026 paper, “CSCO: A Backside-PDN-Aware Clock-Signal Co-Optimization Framework for Improved PPA,” is available as arXiv:2607.13700. Its authors write that, without frontside power-ground shielding, backside power-delivery networks can introduce “severe signal integrity degradation.”

This does not mean backside power delivery is a mistake. It means that moving power changes more than resistance and routing capacity. It also changes the chip’s coupling paths, shielding structures, and electromagnetic environment.

Power Delivery Is Moving

The shift is already underway. Intel’s 18A process uses PowerVia to move coarse-pitch power routing and bumps to the back of the die. TSMC’s A16 process combines nanosheet transistors with its Super Power Rail backside power architecture.

The benefits are substantial. Wider, lower-resistance backside conductors can bring power closer to the transistor while freeing frontside layers for signals. That can reduce IR drop, ease routing congestion and improve power, performance and area.

But frontside power structures were not electrically invisible. In some layouts, power and ground lines also helped shield neighboring signals and constrain coupling.

Removing or relocating them alters the physical design problem.

The Shielding Tradeoff

The CSCO paper argues that backside power-delivery design cannot be optimized independently from clock and signal routing. Traditional frontside power-and-ground strips help maintain favorable capacitance relationships between signal wires. With those strips removed, adjacent nets can couple more directly. A switching signal on an aggressor net may then produce a voltage disturbance or additional delay on a neighboring victim net.

The authors describe the loss of frontside shielding as creating a coupling environment in which crosstalk can increase significantly. Their proposed framework jointly allocates backside resources among power, clock, and signal networks, using selected backside routes to protect signal-integrity-critical paths. That is the genuinely interesting development.

Backside power delivery is not simply a new layer added to an otherwise unchanged design. Power, clocks, signals, and shielding now compete for and interact across both sides of the wafer. The researchers therefore call for cross-layer co-optimization rather than treating each network as a separate design task.

Their results suggest that intelligently routing critical signal and clock nets on the backside can improve timing and signal-integrity robustness without adding conventional shielding overhead. The paper is a preprint, and its findings should not be treated as universal proof across every backside-power architecture. It nevertheless identifies a credible physical-design tradeoff that deserves attention as commercial adoption expands.

Signal Integrity Is Not EMI

It is important not to turn that finding into a broader claim than the evidence supports. Crosstalk, signal integrity, power integrity, and electromagnetic interference are connected, but they are not synonyms.

The CSCO researchers studied coupling noise, timing, and signal integrity inside chip designs. They did not demonstrate that Intel 18A, TSMC A16, or backside-powered chips will generally fail electromagnetic compatibility tests.

A chip can experience internal coupling without generating unacceptable system-level emissions. Conversely, a chip may operate correctly while contributing conducted or radiated noise elsewhere in a package, circuit board, or finished product.

The defensible conclusion is narrower: backside power delivery changes the structures and paths through which electrical disturbances propagate. That makes coordinated analysis of power, signals, clocks and electromagnetic behavior more important—not less.

Another Variable: The Transition Itself

Most approaches to noise control focus on what happens after a digital transition has been generated. Engineers improve routing and return paths. They introduce shielding, filters, decoupling components, and package-level mitigation. The CSCO researchers propose using backside routing itself to shield selected critical nets.

These techniques address where an unwanted signal travels and how strongly it couples. There is another possible design variable: the waveform that produced the spectral content in the first place.

A conventional digital transition moves rapidly between two logic states. The faster and sharper the transition, the more energy the waveform can contain at higher-frequency harmonics. Those harmonics can then enter whatever coupling, interconnect, and return paths the physical architecture provides.

Slip Signal Technologies is developing Spectrally Efficient Digital Logic, or SEDL, to shape the voltage transition between logic states so that less unwanted high-frequency spectral energy is generated by the switching event.

SEDL has not been fabricated or tested on Intel 18A, TSMC A16, or another commercial backside-power process. Slip Signal therefore cannot claim that SEDL resolves the coupling effects identified in the CSCO paper. Any such conclusion would require implementation, measurement, and independent validation.

The technical hypothesis is nevertheless specific and testable. Backside power and routing optimization attempts to improve the paths through which power and signals travel. SEDL is intended to act earlier by modifying the transition that excites those paths.

It would not replace backside power delivery, correct poor routing, or eliminate all forms of crosstalk. It would not remove the need for power-integrity analysis, shielding, filtering or electromagnetic compatibility testing.

Instead, source-level transition shaping could become one additional design lever: reduce the high-frequency content generated by digital switching before engineers must manage its effects elsewhere in the chip, package or system.

A More Complete View of Scaling

The semiconductor industry is no longer scaling only the transistor. Engineers are redesigning power delivery, standard cells, interconnects, clock networks, packages and die-to-die communication. The CSCO paper shows why these changes cannot be evaluated in isolation: moving one network can alter the electrical role previously played by another.

The next step should be to include the switching waveform itself in that co-optimization discussion. Backside power delivery asks how power can reach the transistor more efficiently. Double-sided routing asks how critical signals can avoid congestion and coupling. SEDL asks whether the transition between logic states can generate a cleaner spectrum at the source.

All three questions require substantially more testing before their interactions are understood. But as semiconductor design moves to both sides of the wafer, the industry should examine both sides of the noise equation: how unwanted energy propagates and how much of it is generated in the first place.

Power can move. Noise does not simply disappear.