When One “Chip” Contains 58 Chips, EMI Becomes an Architectural Problem

How many chips can fit inside a chip? According to TSMC, the answer may eventually be 58. At its recent European Technology Symposium, TSMC said its wafer-level integration roadmap could one day combine up to 58 large reticle-sized dies into a single system. That captures one of the semiconductor industry’s biggest shifts. TSMC Article

The future of computing will not be defined only by smaller transistors. It will increasingly depend on assembling enormous numbers of transistors, distributed across many dies, into tightly integrated systems. But putting 58 dies together creates more than a packaging challenge. It creates an electrical neighborhood of unprecedented density.

Each die may contain billions of switching transistors. Compute chiplets can sit beside high-bandwidth memory, analog circuitry, I/O dies, optical engines, and specialized accelerators. They may share interposers, package substrates, power-delivery structures, and high-speed links. The package may look like one component from the outside. Electrically, it could behave more like a crowded city. And in a city that dense, every switching event has neighbors.

The package is becoming the computer

Advanced packaging is no longer just a way to connect a finished chip to a board. It is becoming the architecture itself. Modern AI systems increasingly combine multiple compute dies, memory stacks, and specialized components into a single package. This allows designers to build systems larger than a practical monolithic die while mixing components optimized for different functions. But as more dies are integrated, the design problem expands. Engineers must manage bandwidth, power delivery, heat, and manufacturing yield. They must also manage the electrical disturbance each die introduces into the shared environment.

Rapid voltage and current transitions can generate high-frequency spectral content. Simultaneous switching can disturb shared power and ground networks. Energy can couple through interconnects, substrates, and closely spaced conductors. These effects may appear as jitter, voltage bounce, near-field coupling, substrate noise, or degraded signal integrity. Not all of them are traditional radiated EMI. But they share the same underlying problem: electrical activity in one part of the package can affect another.

With two dies, that may be a layout problem. With 58, it becomes an architectural problem.

Why shielding alone may not be enough

Traditional electromagnetic compatibility techniques remain essential. Engineers use shielding, filtering, careful routing, guard structures, physical separation, and stronger power-delivery networks. But those tools become harder to apply inside a densely integrated package. Separation consumes valuable space. Shielding adds complexity. Filters can introduce area, power, or performance trade-offs. Most importantly, an external enclosure cannot correct a disturbance that has already affected a neighboring circuit inside the package. In addition to containing electrical noise, advanced packages may need to reduce the amount generated at the source.

Can digital logic become a quieter neighbor?

Slip Signal Technologies is developing Spectrally Efficient Digital Logic, or SEDL. The concept is to shape digital transitions differently from conventional abrupt switching.

The working hypothesis is that smoother transitions may reduce unnecessary high-frequency spectral content while preserving the information carried by the signal.

SEDL is not intended to replace shielding, filtering, or signal-integrity engineering. It could potentially provide another tool—one applied before unwanted spectral content spreads through the package. For future multi-die systems, the research questions are direct: 

• Can SEDL reduce high-frequency spectral content under realistic conditions?

• Can it lower the near-field disturbance around switching circuits?

• Can it reduce noise coupled into nearby components or shared power structures?

• Could quieter switching give package designers more flexibility in placement, routing, and isolation?

These remain engineering hypotheses. They must be measured in silicon.

A system-level problem

Slip Signal Technologies is part of NVIDIA’s Inception startup ecosystem program and is progressing toward its first prototype and exploring the potential relevance of quieter switching for future computing architectures. The conversation reinforced a broader reality: the future of AI hardware is a system problem. Processor performance cannot be separated from memory, packaging, power, cooling, networking, or electrical behavior.

Participation in NVIDIA Inception does not constitute NVIDIA validation or endorsement of Slip Signal’s technology, and the conversation should not be interpreted as a technical evaluation of SEDL. It does, however, underscore the relevance of the problem we are investigating.

The semiconductor industry has spent decades learning how to place more transistors on a die. It is now learning how to place more dies inside a system. As one “chip” begins to contain dozens of chips, designers must ask not only how those components connect, but how they coexist. In the electronic cities and data centers now emerging, quieter switching may become part of good architectural planning.